02-19-2012, 11:56 AM
(02-19-2012, 07:41 AM)hlide Wrote:the scePower says that:(02-18-2012, 08:08 PM)bugmenot Wrote: I see, I suppose there's no tricky timing issue on PSP like PS2 does?
Not by the time I rewrote Allegrex core interpreter. For what I remember, we never deal with machine cycles. I think the timing given in scePower is jsut to return some valid values when a game queries which frequencies are.
And psp unlike ps2 doesn't let you to mess with hardware, so you could say there's no tricky timing issue.
// PLL clock:
// Operates at fixed rates of 148MHz, 190MHz, 222MHz, 266MHz, 333MHz.
// Starts at 222MHz.
protected int pllClock = 222;
// CPU clock:
// Operates at variable rates from 1MHz to 333MHz.
// Starts at 222MHz.
// Note: Cannot have a higher frequency than the PLL clock's frequency.
protected int cpuClock = 222;
// BUS clock:
// Operates at variable rates from 37MHz to 166MHz.
// Starts at 111MHz.
// Note: Cannot have a higher frequency than 1/2 of the PLL clock's frequency
// or lower than 1/4 of the PLL clock's frequency.
protected int busClock = 111;